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ks57 c 21408 / c2 1418/p21408 product overvie w 1- 1 1 product overview overview the ks57c21408/c21418/p21408 is a sam47 core-based 4-bit cmos single-chip microcontroller. it has a timer/counter and lcd drivers. the KS57P21408 is especially suited for use in data bank, telephone and lcd general purpose. it is built around the sam47 core cpu and c ontains rom, ram, 39 i/o lines , programmable timer/counter, buzzer output, enough lcd dot matrix, and segment drive pins. the ks57c21408/c21418/p21408 can be used for dedicated control functions in a variety of applications, and is especially designed for multi data bank , telephone and lcd game. otp the ks57c21408/c21418 microcontroller is also available in otp (one time programmable) version, KS57P21408. KS57P21408 microcontroller has an on-chip 8 k-byte one-time- programable eprom instead of masked rom. the KS57P21408 is comparable to ks57c21408/c21418, both in function and in pin configuration.
product overview ks57 c 21408 / c2 1418/p21408 1- 2 features summary memory ? 8192 8 bit program memory ? 5120 4 bit data memory in ks57c21408 ? 2560 x 4 bit data memory in ks57c21418 ? 108 x 5 bit display memory 39 i/o pins ? input: 6 pins ? i/o: 17 pins ? output: maximum 16 pins for 1-bit level output (sharing with segment driver outputs) 8-bit basic timer ? four internal timer functions 8-bit timer /counter 0 ? programmable 8-bit timer ? external event counter ? arbitrary clock frequency output ? external clock signal divider watch timer ? time interval generation: 0,5ms, 3,9ms at 32768hz ? 4 frequency (2/4/8/16 khz) outputs to buz pin interrupts ? three external vectored interrupts: int0, int1, intp0 ? two internal vectored interrupts: intb, intt0 ? two quasi-interrupts: i ntw, int2 memory mapped i/o structure lcd display ? 12 characters dot matrix display (5 x 7) ? 12 digit display (8 segments) ? 60 segments and 9 common pins power-down modes ? idle mode (only cpu clock stops) ? stop mode (main-system clock and cpu clock stops) oscillation sources ? crystal, ceramic, or external rc for system clock ? main - system clock frequency: 0.4 mhz - 6 mhz ? sub - system clock frequency: 32 , 768khz ? cpu clock divider circuit (by 4,8 , or 64) instruction execution times ? 0.67, 1.33, 10.7 s at 6mhz ? 0.95, 1.91, 15.3 s at 4.19 mhz ? 122 s at 32.768 k hz operating temperature ? -45 c to 85 c operating voltage range ? 1.8 v to 5.5 v package type ? 100 - pin qfp package
ks57 c 21408 / c2 1418/p21408 product overview 1- 3 block diagram program status word stack pointer arithmetic and logic unit instruction decoder internal interrupts reset interrupt control block instruction register clock 8 k byte program memory data and display memory p6.0-p6.3/ ks0-ks3 p7.0-p7.3/ ks4-ks7 i/o port 7 i/o port 6 p5.0-p5.3 p4.0/tcl0 p4.1/tclo0 p4.2 i/o port 5 i/o port 4 i/o port 2 p2.0/buz p2.1/clo input port 1 p1.0/int0 p1.1/int1 input port 0 p0.0-p0.3/ k0-k3 output port 8 8-bit timer/ counter 0 program counter watch timer basic timer lcd driver/ controller xt out x out xt in x in p8.0-p8.15/ seg0-seg15 com0-com8 seg16-seg59 seg0-seg15 /p8.0-p8.15 intt0, intb, intw int0, int1, intp0, int2 note: data memory: 2560 x 4 bits in ks57c21418 display memory: 108 x 5 bits 5120 x 4 bits in ks57c21408 figure 1-1. ks57c21408/c21418/p21408 specified block diagram
product overview ks57 c 21408 / c2 1418/p21408 1- 4 pin assignments ks57c21408/c21418 100-qfp 1420c 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 seg59 com4 com5 com6 com7 com8 p6.0/ks0 p6.1/ks1 p6.2/ks2 p6.3/ks3 p7.0/ks4 p7.1/ks5 p7.2/ks6 p7.3/ks7 v dd v ss xout xin test xtin xtout reset p2.0/buz p2.1/clo p5.0 p5.1 p5.2 p5.3 tcl0/p4.0 tclo0/p4.1 seg8/p8.8 seg7/p8.7 seg6/p8.6 seg5/p8.5 seg4/p8.4 seg3/p8.3 seg2/p8.2 seg1/p8.1 seg0/p8.0 com3 com2 com1 com0 int0/p1.0 int1/p1.1 p0.0/k0 p0.1/k1 p0.2/k2 p0.3/k3 p4.2 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15/p8.15 seg14/p8.14 seg13/p8.13 seg12/p8.12 seg11/p8.11 seg10/p8.10 seg9/p8.9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 seg39 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 seg55 seg56 seg57 seg58 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 figure 1-2. ks57c21 4 08 /c21418 pin assignment diagram
ks57 c 21408 / c2 1418/p21408 product overview 1- 5 pin descriptions table 1- 1 . pin descriptions pin name pin type description circuit type pin number share pin p0.0 - p0.3 i 4-bit input port. 1 and 4-bit read , and test are possible. pull - up register s . a-1 35 - 32 k0-k3 p1.0 p1.1 i 2 - bit input port. 1 and 4- bit read , and test are possible, 2 - bit pull - up resistor s are assignable by software. a-3 37 3 6 int0 int1 p2.0 p2.1 i/o 2 - bit i/o port. 1 and 4- bit read/write , and test are p ossible. each individual pin can be specified as input or output. 2 - bit pull - up resistors are assignable by software. pull-up resistors are automatically disabled for output pins. d 23 24 buz clo p4.0 p4.1 p4.2 p5.0 - p5.3 i/o 4-bit i/o port. 1, 4 , and 8- bit read/write , and test are possible. 4-pin unit can be specified as input or output. 4-bit pull-up resistors are assignable by software. pull-up resistors are automatically disabled for output pins. individual pins are software configurable as open- drain or push-pull output. e e-1 e-1 e-1 29 30 31 25 -2 8 tcl0 tclo0 p6.0 - p6.3 i/o 4 -bit i/o port. 1, 4,and 8-bit read/write , and test are possible . each individual pin can be specified as input or output. 4 - bit pull - up resistors are assignable by software. pull-up resistors are automatically disabled for output pins. d-1 7 -1 0 ks0 - ks3 p7.0 - p7.3 4-bit i/o port. 1, 4 , and 8- bit read/write , and test are possible. 4-pin unit can be specified as input or output. 4-bit pull-up resistors are assignable by software. pull-up resistors are automatically disabled for output pins. 1 1 -1 4 ks4 - ks7 p8.0 - p8.15 o 4-bit controllable output. (dual function as segment output pins) h-9 42- 5 7 seg0 - seg15 seg16 - seg59 lcd segment display signal output. h-10 58- 100 , 1 - seg0 - seg15 lcd segment display signal output. h-9 4 2 - 57 p8.0 - p8.15 com0 - com8 lcd common signal output. h-11 38 -4 1 2 - 6 - int0 - int1 i external interrupts. the triggering edge for int0, and int1 is selectable 3 7 -3 6 p1.0 - p1.1 ks0 - ks7 i/o quasi-interrupt input for falling edge detection. 7 -1 4 p6.0 - p7.3 k0 - k3 i vector interrupt input k0 - k3: falling edge detection 35-32 p0.0 - p0.3
product overview ks57 c 21408 / c2 1418/p21408 1- 6 table 1- 1 . pin descriptions (continued) pin name pin type description circuit type pin num. share pin buz i/o 2,4, 8 k hz or 16khz frequency output for buzzer signal. - 23 p2.0 clo clock output - 24 p2.1 x in , x out - crystal, ceramic or rc oscillator pins for main system clock. - 18 , 17 - xt in , xt out - crystal oscillator pins for sub-system clock. - 20 , 21 - tcl0 i/o external clock input for timer/counter 0 - 29 p4.0 tclo0 i/o timer /counter 0 clock output - 30 p4.1 reset i reset input (a ctive low). b 22 - v dd - power supply. - 15 - v ss - ground. - 16 - test i test input: it must be connected to v ss - 19 -
ks57 c 21408 / c2 1418/p21408 product overview 1- 7 pin circuit diagrams vss v dd p-channel in n-channel figure 1-3. pin circuit type a in v dd pull-up p-channel pull-up resistor enable figure 1-4. pin circuit type a-1 v dd in schmitt trigger p-channel pull-up resistor pull-up resistor enable figure 1-5. pin circuit type a-3 v dd in schmitt trigger pull-up register figure 1-6. pin circuit type b
product overview ks5 7 c 21408 / c2 1418/p21408 1- 8 v dd p-channel data output disable n-channel out v ss figure 1-7 . pin circuit type c v dd p-channel pull-up resistor pull-up resistor enable data output disable in/out type c figure 1-8 . pin circuit type d v dd p-channel pull-up resistor pull-up resistor enable data output disable in/out type c schmitt trigger figure 1-9. pin circuit type d- 1 data output disable v dd p - channel pull-up resistor enable n-channel pne v dd pull-up resistor i/o schmitt trigger figure 1- 1 0 . pin circuit type e
ks57 c 21408 / c2 1418/p21408 product overview 1- 9 data output disable v dd p - c hannel pull-up resistor enable n-channel pne v dd pull-up resistor i/o figure 1-11. pin circuit type e-1 v lc2 v lc0 vss seg data/p8.0-p8.15 out key strobe figure 1- 1 2 . pin circuit type h -9 v lc2 v lc0 out segment data figure 1- 1 3. pin circuit type h-10 vss vss out v lc1 com data polarity v dd figure 1- 1 4. pin circuit type h-11
product overview ks5 7 c 21408 / c2 1418/p21408 1- 10 notes
ks57c21 4 08/ c21418/p 21 4 08 electrical data 13? 1 13 electrical data overview in this section, information on ks57c21408/c21418/p21408 electrical characteristics is presented as tables and graphics. the information is arranged in the following order: standard electrical characteristics ? absolute maximum ratings ? d.c electrical characteristics ? main-system clock oscillator characteristics ? sub-system clock oscillator characteristics ? i/o capacitance ? a.c electrical characteristics ? operating voltage range miscellaneous timing waveforms ? a.c timing measurement point ? clock timing measurement at x in ? clock timing measurement at xt in ? tcl0 timing ? input timing for reset ? input timing for external interrupts stop mode characteristics and timing waveforms ? ram data rete ntion supply voltage in stop mode ? stop mode release timing when initiated by reset ? stop mode release timing when initiated by an interrupt request
electrical data ks57c21 4 08/ c21418/p 21 4 08 13? 2 table 13 - 1 . absolute maximum ratings (t a = 25 c) parameter symbol conditions rating units supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i p ort s 0, 1, 2, 4, 5 , 6, 7 ? 0.3 to v dd + 0.3 v output voltage v o ? ? 0.3 to v dd + 0.3 v high level i oh one pin ? 15 ma output current all output pins ? 30 ma low level i ol one pin peak value 30 ma output current rms value ( note ) 15 ma all p ins peak value 100 ma rms value ( note ) 60 ma operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c note : rms value = peak value duty . table 13-2. d.c characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min. typ. max. units input h igh vih1 p ins except below 0. 7 v dd ? v dd v voltage vih2 port 0, 1, 6, 7, p4.0, reset 0. 8 v dd ? v dd vih 3 x in , x out and xt in v dd ? 0. 1 ? v dd input low vil1 all input pins except below ? ? 0. 3 v dd voltage vil2 port 0, 1, 6, 7, p4.0, reset ? 0. 2 v dd vil3 x in ,x out and xt in ? 0. 1 output high voltage voh1 v dd = 4.5 v to 5.5 v port2, 4, 5, 6, 7 i oh = ? 1ma v dd ? 1.0 ? ?
ks57c21 4 08/ c21418/p 21 4 08 electrical data 13? 3 table 13-2. d.c characteristics(continued) (t a = ? 40 c to + 85c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min. typ. max. units output low voltage v ol1 v dd = 4.5 v to 5.5 v port 2, 4, 5 , 6, 7 i ol = 15ma ? ? 2 v dd = 1.8 v to 5.5 v i ol =1 .6 ma ? ? 0.4 in put high leakage current i lih 1 vin = v dd all input pins except below ? ? 3 m a i lih2 vin = v dd x in , x out , xt in 20 in put low leakage current i lil1 v in = 0 v all input p ins except x in , x out , xt in and reset ? ? ? 3 i lil2 v in = 0 v x in , x out , xt in ? ? ? 20 output high leakage current i loh 1 v o = v dd port 2, 4, 5 , 6, 7 ? ? 3 output low leakage current i lol 1 v o = 0 v port 2, 4, 5 , 6, 7 ? ? ? 3 pull-up resistor rl1 v dd = 5 v , v in = 0 v all p ins except reset 25 50 100 k w v dd = 3 v 50 100 200 rl2 v dd = 5 v , v in = 0 v reset 100 250 400 v dd = 3 v 200 500 800 medium output v om1 com0 - com8 vm1 ? 0.2 vm1 vm1 + 0.2 v voltage (1) v om2 com0 - com8 vm2 ? 0.2 vm2 vm2 + 0.2 v om3 seg0 - cseg59 vm3 ? 0.2 vm3 vm3 + 0.2 v om4 seg0 - cseg59 vm4 ? 0.2 vm4 vm4 + 0.2 high output roh1 v o = v dd ? 0.5v seg0 - seg59 ? ? 90 k w impedance roh2 c om0 - com8 ? ? 25 low output rol1 vo = 0.5v seg0 - seg59 ? ? 90 k w resistor rol2 seg0 - seg15 (key strobe) ? ? 2 rol3 com0 - com8 ? ? 25
electrical data ks57c21 4 08/ c21418/p 21 4 08 13? 4 table 13-2. d.c characteristics (continued) (t a = ? 40 c to + 85c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min. typ. max. units supply current (2) (3) idd1 run mode : v dd = 5 v 10% 6mh z ? 5.1 8 ma c rystal oscillator c1 = c2 = 22pf 4.19mhz 3.8 6 v dd = 3 v 10% 6mh z 2.5 4 4.19mhz 1.8 3 i dd2 idle mode : v dd = 5 v 10% 6mh z 1.3 2.5 c rystal oscillator c1 = c2 = 22pf 4.19mhz 1.1 1.8 v dd = 3 v 10% 6mh z 0.5 1.5 4.19mhz 0.4 1.0 idd3 run mode: v dd = 3 v 10% 32khz crystal oscillator ? 30 45 m a idd4 idle mode: v dd = 3 v 10% 32khz crystal oscillator lcd on (4) ? 17 30 v dd = 3 v 10% 32khz crystal oscillator lcd off 6 15 idd5 stop mode ; v dd = 5 v 10% , xt in = 0v ? 2.4 5 stop mode ; v dd = 3 v 10% , xt in = 0v 0.6 3 notes: 1. vm1=2.75/3.75 v dd , vm2=1/3.75 v dd , vm3=2/3.75 v dd , vm4=1.75/3.75 v dd 2. supply curre nt does not include current drawn through internal pull-down resistor a nd lcd driving resistors. 3. for d.c. electrical voltages , pcon register must be set to 0011b. 4 . the mode of i dd 4 (lcd on) is normal.
ks57c21 4 08/ c21418/p 21 4 08 electrical data 13? 5 table 13 - 3 . main system clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units ceramic oscillator x in c1 c2 x out oscillation frequency ( fx) (1) ? 0.4 ? 6.0 mhz stabilization time (2) after v dd reaches the minimum level of its variable range ? ? 4 ms crystal oscillator x in c1 c2 x out oscillation frequency ( fx) (1) ? 0.4 ? 6 mhz stabilization time (2) v dd = 4.5 v to 5.5 v ? ? 10 ms v dd = 1.8 v to 5.5 v ? ? 60 external clock x in x out x in input frequency ( fx) (1) ? 0.4 ? 6 mhz x in input high and low level width (t xh , t xl ) ? 83.3 ? 1250 ns rc oscillator x in x out r frequency v dd = 5 v ? 2 ? mhz v dd = 3 v ? 1 ? notes: 1. oscillation frequency and input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillat or stabilization after a power-on or release of stop mode.
electrical data ks57c21 4 08/ c21418/p 21 4 08 13? 6 table 13-4 . recommended oscillator constants (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v ) manufacturer series number (1) frequency range load cap ( pf) oscillator voltage range (v) remarks c1 c2 min max tdk fcr ? e ? m5 3.58 mhz?6.0 mhz 33 33 2.0 5.5 leaded type fcr ? e ? mc5 3.58 mhz?6.0 mhz (2) (2) 2.0 5.5 on-chip c leaded type ccr ? e ? mc3 3.58 mhz?6.0 mhz (3) (3) 2.0 5.5 on-chip c smd type note s: 1. please specify normal oscillator frequency. 2. on-chip c: 30pf built in. 3. on-chip c: 38pf built in.
ks57c21 4 08/ c21418/p 21 4 08 electrical data 13? 7 table 13 -5 . subsystem clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units crystal oscillator xt in c1 c2 xt out oscillation frequency (1) ? 32 32.768 35 k hz stabilization time (2) v dd = 4.5 v to 5.5 v ? 1.0 2 ms v dd = 1.8 v to 5.5 v ? ? 10 external clock xt in xt out x t in input frequency (1) ? 32 ? 100 k hz x t in input high and low level width (t x t h , t x t l ) ? 5 ? 15 m s notes: 1. oscillation frequency and input frequency data are for oscillator charac teristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on or release of stop mode . table 13 -6 . input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output capacitance c out ? ? 15 pf i/o capacitance c io ? ? 15 pf
electrical data ks57c21 4 08/ c21418/p 21 4 08 13? 8 table 13 -7 . a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units instruction cycle time (note) t cy v dd = 2.7 v to 5.5 v 0. 67 ? 64 s v dd = 1.8 v to 5 .5 v 1.33 with sub-system clock ( fxt) 114 122 1952 tcl0 input frequency f ti v dd = 2.7 v to 5.5 v 0 ? 1 .5 mhz v dd = 1.8 v to 5 .5 v 1 khz tcl0 input high, low width t tih t til v dd = 2.7 v to 5.5 v 0.48 ? ? s v dd = 1.8 v to 5 .5 v 1.8 external interrupt input high, low width t inth , t intl int0, int1, ks0 - ks7 10 ? ? s ks0 - ks3 10 reset low level width t rsl ? 10 ? ? s note: unless otherwise specified, the values of instruction cycle time condition assume a main-system clock ( fx) source.
ks57c21 4 08/ c21418/p 21 4 08 electrical data 13? 9 cpu c lock = 1/n x oscillator frequency (n = 4, 8, 64) 1 2 3 4 5 6 7 supply voltage(v) 0.75 mhz 1.5 mhz 15.625 khz cpu clock 400 khz 3 mhz 6 mhz main oscillator frequency 1.8 v figure 13 - 1. standard operating voltage range table 13 -8 . ram data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 1.8 ? 5.5 v data retention supply current i dddr v dddr = 1.8 v ? 0.1 10 a release signal set time t srel ? 0 ? ? s oscillator stabilization wait time (1) t wait released by reset ? 2 17 / fx ? ms released by interrupt ? (2) ? notes : 1. during oscillator stabilization time, all cpu operations are stopped to avoid unstable operation upon oscillation start. 2. t he basic timer mode register (bmod) interval timer delay s execution of cpu instructions during the wait time.
electrical data ks57c21 4 08/ c21418/p 21 4 08 13? 10 timing waveforms t srel t wait v dd reset execution of stop instruction v dddr data retention mode stop mode internal reset operation idle mode operating mode figure 13 - 2. stop mode release timing when initiated by reset v dd execution of stop instruction v dddr data retention mode stop mode t wait t srel idle mode normal operating mode power-down mode terminating signal (interrupt request) figure 13 - 3. stop mode release timing when initiated by interrupt request
ks57c21 4 08/ c21418/p 21 4 08 electrical data 13? 11 measurement points 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd figure 13 - 4. a.c. timing measurement points (except for x in and xt in ) xin (xtin) t xl ( t xtl) t xh ( t xth) 1 / fx (1 / fxt) v dd ? 0.5 v 0.4 v figure 13 - 5. clock timing measurement at x in and xt in
electrical data ks57c21 4 08/ c21418/p 21 4 08 13? 12 tcl0 t til t tih 1 / f ti 0.8 v dd 0.2 v dd figure 13 -6 . tcl0 timing reset trsl 0.2 v dd figure 13 -7 . input timing for reset signal int0, 1 intp0 ks0 to ks7 t intl t inth 0.8 v dd 0.2 v dd figure 13 -8 . input timing for external interrupts and quasi-interrupts
ks57c21408/c21418/p21408 mechanical data 1 4- 1 1 4 mechanical data overview this section contains the following information about the device package: ? package dimensions in millimeters ? pad diagram ? pad/pin coordinate data table 100-qfp-1420c #100 #1 note : dimensions are in millimeters. 20.00 0.2 14.00 0.2 17.90 0.3 23.90 0.3 0.10 max 0.65 (0.83) 0.10 max (0.58) 0.80 0.20 0.05 min 2.65 0.10 3.00 max 0.15 +0.10 -0.05 0-8 0.3 0.1 0.80 0.20 figure 1 4- 1. 100-qfp -1420 package dimensions
mechanical data ks57c21408/c21418/p21408 1 4- 2 notes
ks57c21408/c21418/p21408 KS57P21408 otp 15- 1 15 KS57P21408 otp overview the KS57P21408 single-chip cmos microcontroller is the otp (one time programmable) version of the ks57c21408/c21418 microcontroller. it has an on-chip otp rom instead of masked rom. the eprom is accessed by serial data format. the KS57P21408 is fully compatible with the ks57c21408/c21418, both in function and in pin configuration. because of its simple programming requirements, the KS57P21408 is ideal for use as an evaluation chip for the ks57c21408/c21418.
KS57P21408 otp ks57c21408/c21418/p 21408 15- 2 KS57P21408 100-qfp 1420c 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 seg59 com4 com5 com6 com7 com8 p6.0/ks0 p6.1/ks1 p6.2/ks2 p6.3/ks3 p7.0/ks4 p7.1/ks5 sdat / p7.2/ks6 sclk /p7.3/ks7 v dd /v dd v ss / v ss xout xin v pp / test xtin xtout reset / reset p2.0/buz p2.1/clo p5.0 p5.1 p5.2 p5.3 tcl0/p4.0 tclo0/p4.1 seg8/p8.8 seg7/p8.7 seg6/p8.6 seg5/p8.5 seg4/p8.4 seg3/p8.3 seg2/p8.2 seg1/p8.1 seg0/p8.0 com3 com2 com1 com0 int0/p1.0 int1/p1.1 p0.0/k0 p0.1/k1 p0.2/k2 p0.3/k3 p4.2 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15/p8.15 seg14/p8.14 seg13/p8.13 seg12/p8.12 seg11/p8.11 seg10/p8.10 seg9/p8.9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 seg39 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 seg55 seg56 seg57 seg58 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 figure 15-1. KS57P21408 pin assignments (100-qfp package)
ks57c21408/c21418/p21408 KS57P21408 otp 15- 3 table 15-1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p3.1 sdat 13 i/o serial data pin. output port when reading and input port when writing. can be assigned as a input / push-pull output port. p3.0 sclk 14 i/o serial clock pin. input only pin. test v pp (test) 19 i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset reset 22 i chip initialization v dd / v ss v dd / v ss 15/16 i logic power supply pin. v dd should be tied to +5 v during programming. table 15-2. comparison of KS57P21408 and ks57c21408/c21418 features characteristic KS57P21408 ks57c21408 program memory 8 kbyte eprom 8 kbyte mask rom operating voltage (v dd ) 1.8 v to 5.5 v 1.8 v to 5.5v otp programming mode v dd = 5 v, v pp (test)=12.5v pin configuration 100 qfp 100 qfp eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the KS57P21408, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 15-3 below. table 15-3. operating mode selection criteria v dd vpp (test) reg/ mem address (a15-a0) r/ w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note : "0" means low level; "1" means high level.
KS57P21408 otp ks57c21408/c21418/p 21408 15- 4 table 1 5 - 4. d.c characteristics (t a = ? 40 c to +85c, vdd = 1.8 v to 5.5 v) parameter symbol conditions min. typ. max. units supply current (2)(3) i dd1 run mode : v dd =5v10% 6mh z ? 5.1 8 ma c rystal oscillator c1=c2=22pf 4.19mhz 3.8 6 v dd = 3v 10% 6mh z 2.5 4 4.19mhz 1.8 3 i dd2 idle mode : v dd =5v10% 6mh z 1.3 2.5 c rystal oscillator c1=c2=22pf 4.19mhz 1.1 1.8 v dd = 3v 10% 6mh z 0.5 1.5 4.19mhz 0.4 1.0 i dd3 run mode : v dd =3v 10% 32khz crystal oscillator ? 30 45 m a i dd4 idle mode : v dd =3v 10% 32khz crystal oscillator lcd on (4) ? 17 30 v dd =3v 10% 32khz crystal oscillator lcd off 6 15 i dd5 stop mode ; v dd =5v10% ? 2.4 5 stop mode ; v dd =3v10% 0.6 3 notes: 1. vm1=2.75/3.75 vdd, vm2=1/3.75 vdd, vm3=2/3.75 vdd, vm4=1.75/3.75 vdd 2. supply current does not include current drawn through internal pull-down resistor a nd lcd driving resistors. 3. for d.c. electrical voltages , pcon register must be set to 0011b. 5 . the mode of i dd4 (lcd on) is normal.
ks57c21408/c21418/p21408 KS57P21408 otp 15- 5 cpu c lock = 1/n x oscillator frequency (n = 4, 8, 64) 1 2 3 4 5 6 7 supply voltage(v) 0.75 mhz 1.5 mhz 15.625 khz cpu clock 400 khz 3 mhz 6 mhz main oscillator frequency 1.8 v figure 1 5-2. standard operating voltage range
KS57P21408 otp ks57c21408/c21418/p 21408 15- 6 notes

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